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2014

Innovaide Opens Design Center in Bengaluru India
Marlborough, MA, June 19, 2014

Bengaluru office underscores growth in India, Southeast Asia and European markets.

Innovaide Inc. announced today the opening of Bengaluru Design Center. The new office in Bengaluru will focus on growing customer base in India and Southeast Asia and European markets. “This will allow us to better serve our global customers having operations and interests in these markets, by being geographically closer to their teams”, said Abhijit Sarid, CEO of Innovaide.

Innovaide provides Product Engineering Services in Data Center, Telecom, Storage, Mobile, Consumer and Healthcare industries. The new office will help deepen our partner relationships and expand our outreach within the new markets. In addition to Product Engineering Services, Innovaide provides reusable Intellectual Property Blocks, Design Verification IPs, Diagnostics and Board bring-up software. The team will also collaborate on technological innovation and Intellectual Properties (IPs) targeted for our customer base in these markets.

2013

Innovaide Join's Cadence Connections Verification Program
Marlborough, MA, January 20, 2013

Innovaide has joined Cadence’s Verification partners program.

Innovaide Inc. announced today that it has joined the Cadence Connections Verification Program. The Connections Program members are selected for their skills and expertise in ASIC Verification technologies and ability to engage successfully with mutual customers.

“The partnership with Cadence provides Innovaide team the ability to handle customer designs in a turnkey fashion with state of the art tools from Cadence. It also allows us to build IPs and technologies that are proven on Cadence tool suite”, according
to Abhijit Sarid, President and CEO of Innovaide.

Innovaide provides design services for design and verification of ASICs from architecture, design, coding in Verilog and VHDL, mapping to appropriate ASIC technologies and optimization for timing and performance. Innovaide also develops and
licenses re-usable Intellectual Property (IP) blocks written in Verilog. These IP blocks can be customized to specific customer requirements as determined by customer design requirements. These blocks are available as Verilog implementation for easy mapping
into any FPGA and ASIC technology

2010

Innovaide Join's Altera's ACAP Partnership Program
Marlborough, MA, June 05, 2010 –

Innovaide has joined Altera’s ACAP partnership program.

Innovaide Inc. announced today that it has joined the Altera Consultants Alliance Program (ACAP). The ACAP members are selected for their technology skills and expertise, quality of work, and ability to engage successfully with mutual customers.

Innovaide provides design services for full turnkey implementation of FPGA’s from architecture, design, coding in Verilog and VHDL, mapping to appropriate FPGA device and optimization for timing and performance. Innovaide also develops and licenses re-usable Intellectual Property (IP) blocks written in Verilog. These IP blocks can be customized to specific customer requirements and mapped to various FPGA technologies as determined by customer design requirements. These blocks are available
as Verilog implementation for easy mapping into any FPGA and ASIC.

“The partnership with Altera provides our customers another level of confidence that Innovaide team has the capability to handle their designs in a turnkey fashion. We are a team that provides local control and management and delivers cost effective
programs through our productivity and close partnerships with the ecosystem”, according to Abhijit Sarid, President and CEO of Innovaide.

2008

Innovaide Licenses Packet Processing and Traffic Management IP
Marlborough, MA, Aug 10, 2008

Innovaide licenses Carrier Grade Classification, Forwarding and Traffic Management IP to Network Equipment Vendor Tejas Networks. The Verilog blocks scale from 5Gig to 40Gig performance in FPGA/ASIC implementations.

Innovaide Inc. announced today that they have licensed their packet processing and traffic management IP targeting the Carrier Ethernet equipment market to a premier Carrier class equipment vendor Tejas Networks Pvt Ltd. The Network Blocks family of reusable Intellectual Property consists of three hardware blocks – Classification Engine, Forwarding Engine, and Traffic Management Engine. These blocks are available as Verilog implementation for easy mapping into any FPGA and ASIC. The efficiently designed architecture allows the blocks to scale performance from 5Gbps up to 40Gbps throughput.

“The solution provides telecom silicon and equipment vendors the ability to add and deploy Metro Ethernet functionality at reduced costs while allowing them todifferentiate by customizing these engines for their requirements. These blocks obviatethe need for using standard off-the-shelf components that are usually more expensive”, according to Abhijit Sarid, President and CEO of Innovaide.

Innovaide Licenses Packet Processing and Traffic Management Ip
Marlborough, MA, June 5, 2008

Innovaide is First-to-Market with licensable Carrier Grade designs for Classification, Forwarding and Traffic Management. The Verilog blocks scale from 5Gig to 40Gig performance in FPGA/ASIC implementations

Innovaide Inc. announced the availability of key packet processing and traffic management engines targeting the Carrier Ethernet equipment market. The SenseNet™ family of reusable Intellectual Property consists of three hardware blocks – Classification Engine, Forwarding Engine, and Traffic Management Engine. These blocks are available as Verilog implementation for easy mapping into any FPGA and ASIC. The efficiently designed architecture allows the blocks to scale performance from 5Gbps up to 40Gbps throughput.

Innovaide provides Verilog and C language based verification environment consisting of test bench and hundreds of test cases. The environment is designed to integrate easily into various customer environments. Innovaide also provides necessary software drivers as well as middleware software to manage configuration and accessibility of hardware functionality by Management Software.

“The solution provides telecom silicon and equipment vendors the ability to add and deploy Metro Ethernet functionality at reduced costs while allowing them to differentiate by customizing these engines for their requirements. These blocks obviate the need for using standard off-the-shelf components that are usually more expensive”, according to Abhijit Sarid, President and CEO of Innovaide.

The proven and thoroughly tested blocks allow a quick turnaround time for customized integration for providing triple and quad play services for carriers. The packet processing and traffic management functions conform to the Metro Ethernet Forum (MEF), IEEE, ITU-T, and IETF specifications.

2006

Cadence Strengthens Verification Alliance Program in India by Adding 13 New Partners
Cadence November 28, 2006

Bangalore, India based Cadence Design Systems (India) Pvt Ltd., the Indian branch of semiconductor design tool leader Cadence Design Systems Inc. reported today that 13 new partners have joined its Verification Alliance Program.

The program is a global partner network of consulting companies with skills in verification consulting services, verification IP development, and training for Cadence customers including GDA Technologies, Ingot Systems, Innovaide, IntelliProp, KPIT Cummins Infosystems, Manipal Dot Net, Mindtree Consulting, nSys, Oski Technology, Silicon Interfaces, StellarIP, Tata Elxsi, and TES PV Electronic Solutions.

eInfochips said it has been part of the program in India for three years and has allowed the company to help its customers be more productive with Cadence technologies, develop verification IP that speeds its customers’ verification process, and reduces the risk associated with incomplete verification.

Through this program, Cadence aims to help its Verification Alliance partners enhance their existing competencies in the Incisive Plan-to-Closure Methodology and Cadence’s verification technologies.

In addition, Verification Alliance partners are able to contribute reusable verification IP to the Cadence OpenChoice IP Program, an online catalog of IP for design and verification.
Jaswinder Ahuja, corporate VP and managing director of Cadence India says there is significant expertise in the area of front-end design and verification in India. The Verification Alliance Program contributes to the Indian semiconductor ecosystem by providing valuable verification resources and market access that will ultimately reduce the risks of getting products to market on time, every time, he said in a statement.

The Verification Alliance Program was launched in 1999 by Verisity Design Systems Inc., a company Cadence acquired in 2005.

With these new partners in India, Cadence says it now has more than 50 partners worldwide with over 500 verification experts addressing customers’ verification challenges.

Innovaide’s Abhijit Sarid on Panel at Tie-Boston's Software Services Business Forum
Marlborough, MA, Jan. 10, 2006

Local Experts to Analyze EDA Industry at Panel Titled, “A New Beginning or Beginning of an End?”

Abhijit Sarid, president of Innovaide Inc., will participate in a panel on the electronic design automation (EDA) industry titled, “A new beginning or beginning of an end?” at TiE-Boston’s Software Services Business Forum (SSBF) Thursday, January 12. The discussion will be held at 6:30 p.m. at the Massachusetts Institute of Technology’s Tang Center in Cambridge, Mass. Admission is $20.

The moderator is Erach Desai of DESAIsive Technology Research who will describe the role EDA tools have played to shrink semiconductor design cycles. In addition to Abhijit, other panelists are Dr. Samuel Fuller, vice president of engineering at Analog Devices, and George Harper, vice president of marketing for BlueSpec Inc. They will attempt to answer the question: Where are the opportunities for entrepreneurs to start and grow new EDA companies in today’s market?

To learn more about the panel or to register to attend, visit: Boston.

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